Verilog-HDL 条件演算子でマルチプレクサ

// ４to１のマルチプレクサを条件演算子で記述
assign out = (sel==0)? in0:
                   (sel==1)? in1:
                   (sel==2)? in2:
                   (sel==3)? in3: 4'bx