Verilog-HDL for/while/repeat文の例

// for/while/repeat文の例
function parity
  input [7:0] data;
  reg   [3:0] sum;
  integer i;
  begin
    sum = 0;

    //for文で記述
    for(i=0; i<8; i=i+1) begin
      sum = sum + data[i];
    end

    //while文で記述
//  while(i<8) begin
//    sum = sum + data[i];
//    i = i+1;
//  end

    //repeat文で記述
//  repeat(8) begin
//    sum = sum + data[i];
//    i = i+1;
//  end

    parity = sum[0];
  end
endfunction