//RAM Model
`define RAM_W (256+8-1)
module SDP_RAM (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
wire clock;
input [7:0] data;
wire [7:0] data;
input [8:0] rdaddress;
wire [8:0] rdaddress;
input [8:0] wraddress;
wire [8:0] wraddress;
input wren;
wire wren;
output [7:0] q;
wire [7:0] q;
reg [7:0] mem[`RAM_W:0];
reg [7:0] sft_1;
reg [7:0] sft_0;
// RAMライト
always
@( posedge clock )
begin :PR_MEM_W
if (wren == 1'b1)
begin
mem[wraddress] <=data[7:0];
end
end
// RAMリード
always
@( posedge clock )
begin :PR_MEM_R
begin
sft_1 <= sft_0;
sft_0 <= mem[rdaddress];
end
end
assign q = sft_1;
endmodule
